1. Technical Field
This disclosure relates to electronic circuits, and more particularly, to circuits for aligning clock and data signals.
2. Description of the Related Art
Integrated circuits (ICs) and electronic systems in general may include multiple functional units in which data signals are exchanged. The data signals may be synchronized by a clock signal that may be sent with the data or generated locally by the receiving functional unit. In some cases, skew may occur between the data signals and clock signals. Such skew may be corrected in some cases by alignment circuits.
Two types of circuits commonly used for performing phase alignment between data signals and clock signals are phase locked loops (PLLs) and delay locked loops (DLLs). Both types of these circuits may implement an analog phase detector and closed loop feedback. A PLL may include a voltage-controlled oscillator (VCO), while a DLL may include a voltage-controlled delay line (VCDL). These types of phase alignment circuits may incrementally adjust the phase difference between a clock signal and a data signal (or more generally, any two signals for which phase alignment is desirable) over time. Typically, such circuits may sample a phase difference at a single point in time and make an incremental adjustment to the phase difference. The feedback loop may be used to provide each sample, after which incremental adjustments may continually be made until the signals are in the desired phase alignment.